1. Field of the Invention
The present invention relates to a memory controller and a memory control method. In particular, the present invention relates to a memory controller supporting a burst transfer and a memory control method based on a burst transfer.
2. Description of the Related Art
In recent years, a DRAM (Dynamic Random Access Memory) capable of data inputting/outputting in synchronization with a clock signal, so-called an SDRAM (Synchronous DRAM) has become a mainstream of the RAM, since it allows for incorporation of a high-speed large-capacity memory into the system. The SDRAM has a burst mode in which data are input/output successively and is configured to enable the data input/output at a high-speed. In order to fully utilize such a high-speed access performance of the SDRAM, an interface circuit is necessary for connection with the SDRAM.
For example, Japanese Laid Open Patent Application JP-P2005-141682 discloses a high-speed memory access control device which controls access to a high-speed memory supporting a burst access. Described in the patent document is a case where a designated number of words are successively input/output by the burst access and there exists a page boundary of the memory during the burst access.
The high-speed memory access control device has an exceptional access information determining means, an address generating means, a switch control means and a timing control means. Based on the number of burst words and an access start address supplied from the outside, the exceptional access information determining means judges that the burst access is an exceptional access extending over successive two pages. In addition, the exceptional access information determining means determines the number of access words to be burst accessed with respect to each of the two pages. The address generating means generates a start address of the high-speed memory from which the burst access is started for each page. In addition, the address generating means changes the start address for switching the page to be accessed from the initial page to the next page. When it is judged that the burst access extends over the successive two pages, the switch control means controls the timing of changing the start address by the address generating means, based on the determined number of access words. The timing control means controls the access timing such that the burst access to the high-speed memory is started after the exceptional access information determining means judges the exceptional access and determines the number of access words.
An SDRAM is used as, for example, a main memory of a microprocessor system. FIG. 1 is a block diagram schematically showing a typical microprocessor system. A data writing operation in the microprocessor system based on a burst transfer will be described with reference to FIG. 1.
As shown in FIG. 1, the microprocessor system is provided with a CPU (Central Processing Unit) 11, a DMAC (Direct Memory Access Controller) 12, an input/output unit (I/O) 18, an SDRAM controller 17 and an SDRAM 20. The CPU 11, the DMAC 12, the SDRAM controller 17 and the input/output unit 18 are often integrated on one chip due to improvement in the integration degree of integrated circuits. In many cases, the microprocessor system is composed of two chips of a chip 10 and the SDRAM 20.
The CPU 11, the DMAC 12, the SDRAM controller 17 and the input/output unit 18 are connected with each other through a bus 15. The CPU 11 accesses the SDRAM 20 that is the main memory, executes a program, receives data from the input/output unit 18, and outputs data to the input/output unit 18. The DMAC 12 controls data transfer between memories and between memory input/output units without through the CPU 11. The SDRAM controller 17 controls the access to the SDRAM 20 by the CPU 11 or the DMAC 12.
As shown in FIG. 2, the SDRAM controller 17 includes a command buffer 91, a data write counter 97, a burst length judgment circuit 95, a burst timing control circuit 96, a data buffer 98 and a data read counter 99. A case of data writing to the SDRAM 20 will be mainly explained hereafter.
The command buffer 91 receives a command PCMD from the CPU 11 or the DMAC 12 through the bus 15. Also, the command buffer 91 receives a burst length PBL of a data to be transferred and an address PADR of a memory indicating the transfer destination, together with the command PCMD. The received command PCMD, the received burst length PBL and the received address PADR are output to the burst timing control circuit 96. At the same time, the received burst length PBL is output also to the burst length judgment circuit 95.
The data write counter 97 makes a count of the number of write data PDATA received by the data buffer 98, based on a data valid signal DVALD. The count value WCNT is output to the burst length judgment circuit 95. The burst length judgment circuit 95 makes a comparison between the count value WCNT from the data write counter 97 and the above-mentioned burst length PBL from the command buffer 91. If the count value WCNT becomes equal to the burst length PBL, the burst length judgment circuit 95 instructs the burst timing control circuit 96 to initiate a burst transfer.
In response to the instruction to initiate the burst transfer, the burst timing control circuit 96 controls a timing of the data transfer to the SDRAM 20. The burst timing control circuit 96 issues to the SDRAM 20 a command SCMD in accordance with a protocol for the data transfer, specifies a transfer destination address SADR, and instructs the data buffer 98 to output the data. Here, the burst timing control circuit 96 can detect completion of the data transfer by referring to a count value RCNT obtained by the data read counter 99. The number of data that can be burst transferred at a time is previously set in a mode register of the SDRAM 20. When the burst transfer continues, the burst timing control circuit 96 issues the command every number of data that can be burst transferred at a time.
Based on the data valid signal DVALD, the data buffer 98 receives the write data (transfer data) PDATA which are supplied through the bus 15 and are to be written to the SDRAM 20. The received write data PDATA are once stored in the data buffer 98. Then, the write data PDATA are output as data DQ to the SDRAM 20 in response to the instruction of the burst timing control circuit 96.
The data read counter 99 makes a count of the number of data output by the data buffer 98, and outputs the count value RCNT to the burst timing control circuit 96. Further, the data read counter 99 may output a read address to the data buffer 98.
FIG. 3 is a timing chart showing an example of the data writing operation. Referring to FIG. 3, an operation of the SDRAM controller 17 will be explained. It should be noted that the SDRAM controller 17, the bus 15 and the SDRAM 20 operate in synchronization with a clock CLK. A data width of the data supplied to the SDRAM controller 17 through the bus 15 is equal to a data width of the data transferred from the SDRAM controller 17 to the SDRAM 20. Each of reference numerals t0 to t21 (see (a) in FIG. 3) denotes a cycle of the clock CLK and is used for explaining timing. Further, a case is considered where the burst length that the SDRAM 20 can receive at a time is set to “4”.
A command PCMD: WR, which is an instruction to write data to the SDRAM 20, is output to the bus 15 together with a burst length PBL: 8 and an address PADR (see (b) and (c) in FIG. 3). At the clock rising in the cycle t0, the command buffer 91 receives the command PCMD: WR, the burst length PBL: 8 and the address PADR.
During a period from the cycle t1 to the cycle t8, the data valid signal DVALD indicates that the write data PDATA on the bus 15 is valid (see (e) in FIG. 3). During the period from t1 to t8, the data buffer 98 receives the write data PDATA: D0 to D7 (see (d) in FIG. 3). Here, the data write counter 97 makes a count of the number of the received write data PDATA by counting the number of risings of the clock CLK during the period from t1 to t8 when the data valid signal DVALD is activated (see (f) in FIG. 3).
In the present example, the specified burst length is “8”. When the count value WCNT obtained by the data write counter 97 becomes equal to “8”, namely, at the cycle t8, the burst length judgment circuit 95 instructs the burst timing control circuit 96 to initiate the data transfer to the SDRAM 20. In response to the instruction to initiate the data transfer, the burst timing control circuit 96 outputs to the SDRAM 20 a command SCMD: ACT which instructs the SDRAM 20 to start operation. Here, the burst timing control circuit 96 outputs the command SCMD: ACT such that the SDRAM 20 can receive it at the cycle t10 (see (f) and (h) in FIG. 3).
The burst timing control circuit 96 stands by until the operation of the SDRAM 20 becomes ready. Then, the burst timing control circuit 96 outputs a command SCMD: WR instructing the data writing such that the SDRAM 20 can receive the command SCMD: WR at the cycle t13 (see (h) in FIG. 3). In response to the instruction by the burst timing control circuit 96, the data buffer 98 starts outputting of the stored write data (DQ: D0 to D7) from the cycle t13. The SDRAM 20 receives the command SCMD: WR at the clock rising in the cycle t13. From the clock rising in the next cycle t14, the SDRAM 20 receives the write data (DQ: D0 to D7) in synchronization with the clock CLK (see (h) and (i) in FIG. 3). In synchronization with the data output instruction for the data buffer 98, the data read counter 99 makes a count of the number of data output from the data buffer 98 (see (g) in FIG. 3).
When the data DQ: D3 that is the fourth word is output at the cycle t17, the count value RCNT obtained by the data read counter 99 becomes equal to the burst length “4” set in the mode register of the SDRAM 20. At the same time (cycle t17), the burst timing control circuit 96 outputs to the SDRAM 20 another command SCMD: WR instructing the data writing of the next four words. Since the second command SCMD: WR is output at this timing, the SDRAM 20 is able to receive data successively without receiving a new address.
The output of the second command SCMD: WR means that all commands necessary for the data transfer of the burst length “8” instructed to the SDRAM controller 17 are completely output. Therefore, the command buffer 91 can receive the next command PCMD. In the present example, the command buffer 91 can receive the next command PCMD at the cycle t18.
As for the former data transfer, the count value RCNT obtained by the data read counter 99 becomes “8” at the cycle t21. Therefore, the data read counter 99 notifies the burst timing control circuit 96 that the last data DQ: D7 is output. Thus, the data transfer is completed at this point of time.